M28W160BB100ZB1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M28W160BB100ZB1

16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory

STMicroelectronics 

M28W160BT, M28W160BB

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

able must be at VIL in order to perform a read op-

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 9, Read Mode AC Waveforms, and Table

12, Read AC Characteristics, for details of when

the output becomes valid.

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

and Write Enable are at VIL with Output Enable at

VIH. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

Table 2. Bus Operations

Operation

E

G

W

Read

VIL

VIL

VIH

Write

VIL

VIH

VIL

Output Disable

VIL

VIH

VIH

Standby

VIH

X

X

Reset

X

X

X

Note: X = VIL or VIH, VPPH = 12V ± 5%.

See Figures 10 and 11, Write AC Waveforms, and

Tables 13 and 14, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at VIH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at VIH and the device is in

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

VIH during a program or erase operation, the de-

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity, even if Chip Enable is low, VIL, and the supply

current is reduced to IDD1. The data Inputs/Out-

puts will still output data.

Reset. During Reset mode, when Output Enable

is low, VIL, the memory is deselected and the out-

puts are high impedance. The memory is in Reset

mode when Reset is at VIL. The power consump-

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to VSS during a Pro-

gram or Erase, this operation is aborted and the

memory content is no longer valid.

RP

WP

VPP

DQ0-DQ15

VIH

X

Don't Care

Data Output

VIH

X

VDD or VPPH

Data Input

VIH

X

Don't Care

Hi-Z

VIH

X

Don't Care

Hi-Z

VIL

X

Don't Care

Hi-Z

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