MAQ3693NE View Datasheet(PDF) - Dynex Semiconductor

Part Name

Description

Manufacturer

MAQ3693NE

1553B Bus Controller/Remote Terminal

Dynex Semiconductor 

MA3690/1/3

TX Status Missing

This bit will be set if a no-response is detected from an RT

which has been commanded to transmit and the relevant RT

address was not the Broadcast address.

This bit will be reset at the start of each new instruction

cycle or message retry.

TX Status Flag

This bit will be set if the status word received from a

transmitting RT has a bit set or has the wrong terminal

address.

This bit will be reset at the start of each new instruction

execution cycle or message retry.

This bit will be reset to logic zero when the terminal is reset

or when the terminal detected a quiet bus.

RECEIVE STATUS WORD

The receive status word location is addressed when

CODENN, C1 and R/WN are low and C0 is high. This location

is used by the terminal to store the status word, if any, received

from a receiving RT. In self test mode this location is updated

with the contents of the receive command word during the

instruction fetch cycle.

TRANSMIT STATUS WORD

RX Status Missing

This bit will be set if a no-response is detected from an RT

which has been commanded to receive and the relevant RT

address was not the Broadcast address.

This bit will be reset at the start of each new instruction

cycle or message retry.

The transmit status word location is addressed when

CODENN, C0 and R/WN are low and C1 is high. This location

is used by the terminal to store the status word, if any, received

from a transmitting RT. In self test mode this location is

updated with the contents of the transmit command word

during the instruction fetch cycle.

RX Status Flag

MODES OF OPERATION

This bit will be set if the status word received from a

receiving RT has a bit set or has the wrong terminal address.

This bit will be reset at the start of each new instruction

execution cycle or message retry.

Transmitter Timeout On Bus 0

This bit will be set if the transmitter timeout mechanism

operates on Bus 0. This will be set under Self Test execution

with Bus 0 selected in the Instruction word.

This bit will be reset to logic zero if the terminal is reset.

Transmitter Timeout On Bus 1

The Bus Controller may be controlled in either a single shot

mode or in a table driven mode. In the former, the execution of

the message table would be under direct control of the

subsystem, on a message by message basis.

The table driven mode would provide a subsystem

capable of more autonomous operation, leading to a greatly

reduced level of processor intervention in the message

execution level, at least. In either case the procedure of

Instruction fetch, message execute and reporting would be the

same. The difference arises from the value of the HALTREQN

line when it is resampled at the end of message execution.

This is further described below.

This bit will be set if the transmitter timeout mechanism

operates on Bus 1. This will be set under Self Test execution

with Bus 1 selected in the Instruction word.

This bit will be reset to logic zero if the terminal is reset.

Continuous Bus Traffic

This bit will be set if the terminal detected that the data bus

is already active when the BC is instructed to execute a

message on that data bus. An active data bus is defined as a

data stream of one command word or status word and greater

than 32 continguous data words being received by the

terminal. The setting of this bit will cause transmission to be

suppressed and a subsystem interrupt to be generated.

It should be noted that:

SINGLE SHOT OPERATION

To commence a message execution the subsystem must

take the HALTREQN line low to high for a minimum of 1us.

This will be followed by the terminal acknowledging this action

by the HALTEDN line being set inactive (high). The HALTEDN

line will remain high until the message has been completed, at

which time the HALTREQN line is further sampled. If it is low

then the terminal will halt and wait until the request line is taken

high again, in effect a single instruction execution.

It is important to the integrity of the system that the

HALTREQN line is strictly glitch free, otherwise problems will

arise with the terminal attempting to execute commands at a

time when no terminal access to the various stores can be

guaranteed.

1. This condition is only likely to be caused by a

runaway RT which transmits continuously.

2. If this condition is present the subsystem is able to

specify the use of the alternative bus for its

transmissions.

7/41

Share Link: